Why was the shufflevector translated into ISD::EXTRACT_VECTOR_ELT here instead of ISD::EXTRACT_SUBVECTOR?

I think this is caused by [the code](https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L4199) requiring “Idx" to be aligned to "MaskNumElts", but I’m curious—what would happen if it weren’t aligned?
I think in my test case, translating it into ISD::EXTRACT_SUBVECTOR would also be valid.

reproducer:
; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(argmem: readwrite) vscale_range(16,1024)
define dso_local void @foo(ptr %pout, ptr %pin1, ptr %pin2) {
entry:
%0 = load <16 x float>, ptr %pin1, align 16
%tu.sroa.0.16.vec.extract = shufflevector <16 x float> %0, <16 x float> poison, <8 x i32>
ret void
}

command:
llc -march=riscv64 -mattr=+rvv reproducer.ll --debug

Then get the initial dag result:
Initial selection DAG: %bb.0 'foo:entry'
SelectionDAG has 29 nodes:
t0: ch,glue = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %0
t6: i64,ch = CopyFromReg t0, Register:i64 %2
t7: i64 = Constant<0>
t4: i64,ch = CopyFromReg t0, Register:i64 %1
t9: v16f32,ch = load<(load (s512) from %ir.pin1, align 16)> t0, t4, undef:i64
t10: v16f32 = undef
t12: f32 = extract_vector_elt t9, Constant:i64<4>
t14: f32 = extract_vector_elt t9, Constant:i64<5>
t16: f32 = extract_vector_elt t9, Constant:i64<6>
t18: f32 = extract_vector_elt t9, Constant:i64<7>
t20: f32 = extract_vector_elt t9, Constant:i64<8>
t22: f32 = extract_vector_elt t9, Constant:i64<9>
t24: f32 = extract_vector_elt t9, Constant:i64<10>
t26: f32 = extract_vector_elt t9, Constant:i64<11>
t27: v8f32 = BUILD_VECTOR t12, t14, t16, t18, t20, t22, t24, t26
t28: ch = RISCVISD::RET_GLUE t0