Documentation fails to explain SRWD issue: hardware write protect is currently (mostly) not possible
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Description
The Heads documentation [suggests](https://osresearch.net/Heads-threat-model/#system-firmware):
>Finally, once Coreboot has been flashed into the ROM, the write protect pins on the ROMs can be shorted to ground as an extra layer of protection. This prevents any software re-writes of the ROM, even from the Management Engine or other devices on the SPI bus.
However, this is not as easy as it sounds. Most Thinkpad chips [require extra SRWD bits to be set when flashing](https://github.com/flashrom/flashrom/issues/185) in order for the hardware write protect pins to have any effect. Flashrom doesn't currently support setting these bits, see the [linked issue](https://github.com/flashrom/flashrom/issues/185) for a more in-depth description of what is needed (and a patch for Flashrom).
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the system-firmware section of the Heads threat model and review the linked Flashrom issue for the SRWD limitation. Update the documentation to explain that hardware write protection is not generally effective on the affected ThinkPads without the required bits, and retain the reference to the Flashrom issue for details.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation, security
- Issue type
- Documentation
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100