Optimize 4-way interleaved load/store on x86

NEON has a native instruction for this, but x86 does not, so it has to be emulated.

Right now there is no dedicated AVX2 lowering, it's all just sequences of SSE unpacks. It's almost certainly possible to do better.

#298 addressed the API shortcomings but didn't change performance.

Locate the 4-way interleaved load/store lowering and its current SSE-unpack sequence, then compare it with the NEON implementation and the lack of a dedicated AVX2 lowering. Done means improving the x86 implementation's performance while preserving the API changes addressed by #298 and existing behavior.

Written by the indexing model from the issue text.