Dealing with a transient serial port

I have a zynq_zybo board which has a built-in UART, connected to my lab server via a micro-USB cable. The UART appears when the board powers on and goes away when not.

At present I am seeing this output from labgrid-client:

LG_CROSSBAR=ws://kea:20408/ws labgrid-client  -c /vid/software/devel/ubtest/lab/env_rpi_try.cfg -V do-bootstrap 1 -V do-build 1 -V do-send 0 -p zynq_zybo -s start -a console
Building U-Boot in sourcedir for xilinx_zynq_virt
Writing U-Boot using method zynq
cat: /sys/class/block/sdv1/size: No such file or directory
cat: /sys/class/block/sdv1/size: No such file or directory
cat: /sys/class/block/sdv1/size: No such file or directory
console
Traceback (most recent call last):
  File "/vid/software/devel/ubtest/labgrid/labgrid/remote/client.py", line 1969, in main
    target = session._get_target(place)
  File "/vid/software/devel/ubtest/labgrid/labgrid/remote/client.py", line 681, in _get_target
    strategy.transition(self.args.state)
  File "/vid/software/devel/ubtest/labgrid/labgrid/strategy/ubootstrategy.py", line 91, in transition
    self.target.activate(self.console)  # for zynq_zybo
  File "/vid/software/devel/ubtest/labgrid/labgrid/target.py", line 469, in activate
    self.await_resources(resources)
  File "/vid/software/devel/ubtest/labgrid/labgrid/target.py", line 101, in await_resources
    raise NoResourceFoundError(
labgrid.exceptions.NoResourceFoundError: Not all resources are available: {NetworkSerialPort(target=Target(name='zynq_zybo', env=Environment(config_file='/vid/software/devel/ubtest/lab/env_rpi_try.cfg'), var_dict=None), name='USBSerialPort', state=<BindingState.bound: 1>, avail=False, host='kea', port=None, speed=115200, protocol='rfc2217')}

The word 'console' is printed just before the console is activated (self.target.activate(self.console))

I was expecting that this sort of thing would be handled automatically. Is there a way to make this work?

BTW the labgrid-suggest output is this:

=== added device ===
  USBSerialPort for /devices/pci0000:00/0000:00:1b.0/0000:02:00.0/0000:03:00.2/usb1/1-5/1-5.2/1-5.2.1/1-5.2.1:1.0/ttyUSB7/tty/ttyUSB7
  === device properties ===
  device node: /dev/ttyUSB7
  udev tags: , systemd
  vendor: Digilent
  vendor (DB): Future Technology Devices International, Ltd
  model: Digilent_Adept_USB_Device
  model (DB): FT2232C/D/H Dual UART/FIFO IC
  revision: 0700
  === suggested matches ===
  USBSerialPort:
    match:
      ID_PATH: pci-0000:03:00.2-usb-0:5.2.1:1.0
  ---
  USBSerialPort:
    match:
      ID_SERIAL_SHORT: '210279653540'
      ID_USB_INTERFACE_NUM: '00'
  ---

=== added device ===
  USBSerialPort for /devices/pci0000:00/0000:00:1b.0/0000:02:00.0/0000:03:00.2/usb1/1-5/1-5.2/1-5.2.1/1-5.2.1:1.1/ttyUSB20/tty/ttyUSB20
  === device properties ===
  device node: /dev/ttyUSB20
  udev tags: , systemd
  vendor: Digilent
  vendor (DB): Future Technology Devices International, Ltd
  model: Digilent_Adept_USB_Device
  model (DB): FT2232C/D/H Dual UART/FIFO IC
  revision: 0700
  === suggested matches ===
  USBSerialPort:
    match:
      ID_PATH: pci-0000:03:00.2-usb-0:5.2.1:1.1
  ---
  USBSerialPort:
    match:
      ID_SERIAL_SHORT: '210279653540'
      ID_USB_INTERFACE_NUM: '01'
  ---

so I am using this in my export file:

zynq_zybo:
  location: 'lab'
  USBSerialPort:
    ## ttyusb_port5
    ## hub c1
    match:
      ##'@ID_PATH': 'pci-0000:03:00.2-usb-0:5.2.1:1.1'
      ID_SERIAL_SHORT: 210279653540
      ID_USB_INTERFACE_NUM: 01

  USBSDWireDevice:
    ## sdwire3
    ## hub
    match:
      'ID_SERIAL_SHORT': '202001064001'

  NetworkPowerPort:
    ## dli_main_port1
    model: digitalloggers_http
    host: http://admin:1234@192.168.4.19
    index: 5

  HIDRelay:
    ## usbrelay 0 6
    ##serial: 6QMBS
    index: 6
    usbrelay: True
    match:
      '@ID_PATH': 'pci-0000:00:14.0-usb-0:10.1.2'

although I have tried various things for USBSerialPort

Start with the activation path shown in labgrid/remote/client.py, labgrid/strategy/ubootstrategy.py, and labgrid/target.py, especially target.await_resources() and the USBSerialPort resource state. Reproduce the configuration with the transient UART and inspect how resource disappearance and reappearance are handled. Done means the documented USBSerialPort setup works across board power cycles, or the issue clearly documents the unsupported behavior and required recovery.