kir486680 / kir486680/NeuroCore
Making multiple files at once
Open
- Dominant language
- Verilog
- Stars
- 2
- Forks
- 0
- PR merge metrics
- No merged PRs in 30d
Description
Currently, the make file in my tests folder is able to compile only one simulation at a time. There should be a way to run them all in parallel.
Contributor guide
No contributing guide indexed for this repository
Research direction
Inspect the make file in the tests folder and identify how the simulation targets are currently defined and invoked. Determine how all simulation targets can be compiled in parallel, then verify that the complete test set builds successfully together.
Written by the indexing model from the issue text.
Assessment
- Domain
- build-system, testing
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100