Variable and command substitution

In Makefile we could substitute a command with an variable, and running with alternatives: `make CC=clang++ test`:

```Makefile
CC = g++
test:
$(CC) foo.cc
```

Though this is related to Makefile syntax, it might still be worth to consider it. XD

The issue provides a Makefile example using CC and a test target, but names no implementation file or test. Start by locating Bake's command parsing and execution entry points, then verify that a command variable can be overridden as in `make CC=clang++ test`; done means the documented example works without breaking existing command execution.

Written by the indexing model from the issue text.