jaywcjlove / jaywcjlove/reference
【备忘清单】 请求: verilog
Open
- Dominant language
- Dockerfile
- Stars
- 15.3k
- Forks
- 2.2k
- Avg merge
- 2h 17m
- Merged PRs (30d)
- 4
Description
verilog是一种常用的硬件描述语言,多用于数字芯片设计;支持更丰富描述的system verilog现在也用得很多。
Contributor guide
Research direction
The issue requests a Verilog reference but names no files, tests, or entry point. Start by inspecting the repository’s existing technical cheat sheets and their contribution structure; done means adding a Verilog reference in the established format, including the related SystemVerilog context described in the request.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 30/100