ispc / ispc/ispc

[WASM] Mask handling performance issues

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Codegen Performance
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Description

In ISPC it's common to check for masked lanes using __movmsk to move mask bits from `` to i64 with bit per lane and then do checks on individual bits. That results in sub optimal codegen for WASM target due to the limitations of the ISA. I did some tests and the performance gains are quite visible(-35%) on mandelbrot example. It's achieved by replacing mask comparisons via movmask to i128 bit comparison(masks are changed to <4 x i32>):
```asm
%"finished&funci128.i433" = bitcast <4 x i32> %"finished&func.i432" to i128
%"internal_mask&function_mask12i128.i434" = bitcast <4 x i32> %"internal_mask&function_mask10.i417575" to i128
%"equal_finished&func_internal_mask&function_mask12.i435" = icmp eq i128 %"finished&funci128.i433", %"internal_mask&function_mask12i128.i434"
```
which V8 turns into this x86 code:
```asm
vpextrq rsi,xmm0,0x1
vpextrq r11,xmm5,0x1
vpextrq r14,xmm0,0x0
vpextrq rcx,xmm5,0x0
xor rsi,r11
xor r14,rcx
or rsi,r14
```
instead of this code that is generated with __movmsk approach:
```asm
pand xmm8,xmm2
vpextrd r11d,xmm8,0x1
vpextrd r15d,xmm8,0x2
and r11d,0x1
vmovd r14d,xmm8
and r15d,0x1
shl r11d,1
and r14d,0x1
vpextrd r12d,xmm8,0x3
shl r15d,0x2
or r11d,r14d
shl r12d,0x3
or r15d,r11d
or r12d,r15d
and r12d,0xf
mov r11,QWORD PTR [rbp-0x88]
and r11d,0xf
cmp r12d,r11d
```
Which not only yields to more code but also increases reg pressure. Probably V8 could've done a better job optimizing code but we're left with what we have here.
I think it makes sense to rid some of the code and intrinsics of the explicit use of movmsk.
This isn't useful for x86 target due to MOVMSKPS that does <4xi32> -> i4 truncation in one instruction. But good for WASM simd4 mode because there's only extract_lane.
I'll try to prepare a PR with some measurable improvements.

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