Register linalg__powsum and _foreach_powsum.Scalar for XPU backend

### 🚀 The feature, motivation and pitch

The upstream PyTorch native_functions.yaml defines two new reduction ops linalg__powsum and _foreach_powsum.Scalar with CUDA dispatch but no XPU registration:

```yaml
- func: linalg__powsum(Tensor self, Scalar ord=2, int[1]? dim=None, bool keepdim=False, *, ScalarType? dtype=None) -> Tensor
python_module: linalg
variants: function
dispatch:
CompositeExplicitAutograd: linalg__powsum_slow
CPU, CUDA: linalg__powsum
tags: reduction

- func: _foreach_powsum.Scalar(Tensor[] self, Scalar ord=2, ScalarType? dtype=None) -> Tensor[]
device_check: NoCheck
variants: function
dispatch:
CompositeExplicitAutograd: foreach_tensor_powsum_slow
CUDA: foreach_tensor_powsum_cuda
autogen: _foreach_powsum.Scalar_out
```
We need to add XPU dispatch entries and corresponding kernel implementations to torch-xpu-ops.

Acceptance Criteria:
- [ ] torch.linalg._powsum works correctly on XPU device with the fast kernel path.
- [ ] torch._foreach_powsum works correctly on XPU with the fast fused kernel path.
- [ ] Falls back to slow path for unsupported dtypes (integral, complex) or configurations.
- [ ] Passes upstream op tests with XPU device.

### Alternatives

_No response_

### Additional context

_No response_