Enable FP8/MXFP8 Ops with requests and CUDA alignment

## Summary
This is a tracking issue to enable FP8 and MXFP8 operations on XPU, covering memory ops (fill, flip, index_put, gather, cat, eq, ne, where, empty/zeros/ones, to, copy, clone, add/sub/mul/div, compare, normal) and GEMM ops (_scaled_mm and _scaled_grouped_mm) across multiple FP8 variants (e4m3fn, e4m3fnuz, e5m2, e5m2fnuz, e8m0fnu). The issue tracks support status with green/yellow/red indicators and links to related PRs, targeting PyTorch releases from 2.10 through 2.16.

## Type
- **Category:** feature-gap
- **Platform:** xpu
- **Related Components:** FP8/MXFP8 kernels, memory ops (fill, flip, index_put, index_select, gather, cat, eq, ne, where, empty/zeros/ones, to, copy, clone, add/sub/mul/div, compare, normal), GEMM ops (_scaled_mm, _scaled_grouped_mm)

## Objective
Enable FP8/MXFP8 support for a set of memory and GEMM operations across all FP8 dtype variants (e4m3fn, e4m3fnuz, e5m2, e5m2fnuz, e8m0fnu), with CUDA alignment for scaled matrix multiply ops.

## Current Status
| Memory Op | e4m3fn | e4m3fnuz | e5m2 | e5m2fnuz | e8m0fnu | PR Link |
|------------------------------------|--------|----------|------|----------|---------|----------|
| fill/fill_ | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| flip/fliplr/flipud | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2190 |
| index_put/index_put_ | 🟢 | 🟢 | 🟢 | 🟢 | ❌ | #2190 |
| index.Tensor/index.Tensor_out | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2190 |
| index_select/index_select.out | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| gather/gather.out | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| cat/cat.out | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2152 |
| eq/eq_ | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2152 |
| ne/ne_ | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| where | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2152 |
| empty/zeros/ones | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| to | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| copy | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2258 |
| clone | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| add/sub/mul/div | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | #2145 |
| compare | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | #2154 |
| normal | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | |

| GEMM OP | Activation&Weight | Scale Modeling | Scale data type | Scale layout | Status| PR Link | Targets |
|---------------------|---------------------|-----------------------------------------------|-----------------|---------------|-------|--------|----------|
| _scaled_mm | FP8(E4M3/E5M2) | Tensorwise scaling | FP32 | Scalar | 🟢 |[pt#165978](https://github.com/pytorch/pytorch/pull/165978) | 2.10 |
| | FP8(E4M3/E5M2) | Channelwise scaling | FP32 | Vector | 🟢 |[pt#165978](https://github.com/pytorch/pytorch/pull/165978) | 2.10 |
| | FP8(E4M3/E5M2) | 128-element 1D/128x128-element 2D block scaling | FP32 | Tensor | 🟢 |[pt#173630](https://github.com/pytorch/pytorch/pull/173630) | 2.12 |
| | MxFP8(E4M3/E5M2) | 32-element 1D block scaling | UE8M0 | Tiled Tensor | 🟢 | [pt#181726](https://github.com/pytorch/pytorch/pull/181726) | 2.14 |
| _scaled_grouped_mm | FP8(E4M3/E5M2) | Tensorwise scaling | FP32 | Scalar | 🟡 | | 2.16 |
| | FP8(E4M3/E5M2) | Channelwise scaling | FP32 | Vector | 🟡 | | 2.16 |
| | FP8(E4M3/E5M2) | 128-element 1D/128x128-element 2D block scaling | FP32 | Tensor | 🟡 | | 2.16 |
| | MxFP8(E4M3/E5M2) | 32-element 1D block scaling | UE8M0 | Tiled Tensor | 🟡 | | 2.16 |

## Context
Labels: dtype: float8. Related PRs: #2190, #2152, #2145, #2154, #2258, pytorch/pytorch#165978, pytorch/pytorch#173630. PyTorch release targets range from 2.10 to 2.16.

## Root Cause Analysis
This is a tracking issue (not a bug report) for incrementally enabling FP8 and MXFP8 operations on XPU. Several memory ops (add/sub/mul/div, compare, normal) and GEMM ops (_scaled_mm with block scaling and MXFP8, _scaled_grouped_mm) are partially implemented (🟡) or missing. The gaps are in kernel implementations within torch-xpu-ops for arithmetic/comparison ops on FP8 dtypes, and GEMM ops for advanced scaling modes.

## Proposed Fix Strategy
This is a multi-PR tracking issue. Individual sub-tasks are tracked via linked PRs (e.g., #2145 for add/sub/mul/div, #2154 for compare). Each unfinished item requires separate kernel implementations in torch-xpu-ops. No single agent action closes this issue — it is an umbrella tracker that must be resolved incrementally as sub-PRs land.

## Action Items
- [x] 🔍 Issue formatted (Discovery Agent)
Discovery log

**[2026-05-10 23:05:41]**
**Summary:** This is a tracking issue to enable FP8 and MXFP8 operations on XPU, covering memory ops (fill, flip, index_put, gather, cat, eq, ne, where, empty/zeros/ones, to, copy, clone, add/sub/mul/div, compare, normal) and GEMM ops (_scaled_mm and _scaled_grouped_mm) across multiple FP8 variants (e4m3fn, e4m3fnuz, e5m2, e5m2fnuz, e8m0fnu). The issue tracks support status with green/yellow/red indicators and links to related PRs, targeting PyTorch releases from 2.10 through 2.16.
**Failed tests:** N/A
**Dependency:** N/A
**Commit scope:** N/A

## Original Issue
Original issue body

### 🚀 The feature, motivation and pitch

Plan to enable the following ops for FP8/MXFP8:
🟢 Supported 🟡 TBD ❌Rejected
| Memory Op | e4m3fn | e4m3fnuz | e5m2 | e5m2fnuz | e8m0fnu | PR Link |
|------------------------------------|--------|----------|------|----------|---------|---------|
| fill/fill_ | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| flip/fliplr/flipud | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2190 |
| index_put/index_put_ | 🟢 | 🟢 | 🟢 | 🟢 | ❌ | #2190 |
| index.Tensor/index.Tensor_out | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2190 |
| index_select/index_select.out | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| gather/gather.out | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| cat/cat.out | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2152 |
| eq/eq_ | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2152 |
| ne/ne_ | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| where | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2152 |
| empty/zeros/ones | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| to | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| copy | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | #2258 |
| clone | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | |
| add/sub/mul/div | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | #2145 |
| compare | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | #2154 |
| normal | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | |

| GEMM OP | Activation&Weight | Scale Modeling | Scale data type | Scale layout | Status| PR Link | Targets |
|---------------------|---------------------|-----------------------------------------------|-----------------|---------------|-------|--------|---------|
| _scaled_mm | FP8(E4M3/E5M2) | Tensorwise scaling | FP32 | Scalar | 🟢 |[pt#165978](https://github.com/pytorch/pytorch/pull/165978) | 2.10 |
| | FP8(E4M3/E5M2) | Channelwise scaling | FP32 | Vector | 🟢 |[pt#165978](https://github.com/pytorch/pytorch/pull/165978) | 2.10 |
| | FP8(E4M3/E5M2) | 128-element 1D/128x128-element 2D block scaling | FP32 | Tensor | 🟡 |[pt#173630](https://github.com/pytorch/pytorch/pull/173630) | 2.12 |
| | MxFP8(E4M3/E5M2) | 32-element 1D block scaling | UE8M0 | Tiled Tensor | 🟡 | | 2.14 |
| _scaled_grouped_mm | FP8(E4M3/E5M2) | Tensorwise scaling | FP32 | Scalar | 🟡 | | 2.16 |
| | FP8(E4M3/E5M2) | Channelwise scaling | FP32 | Vector | 🟡 | | 2.16 |
| | FP8(E4M3/E5M2) | 128-element 1D/128x128-element 2D block scaling | FP32 | Tensor | 🟡 | | 2.16 |
| | MxFP8(E4M3/E5M2) | 32-element 1D block scaling | UE8M0 | Tiled Tensor | 🟡 | | 2.16 |

### Alternatives

_No response_

### Additional context

_No response_

triage log
**Verdict:** NEEDS_HUMAN
**Reason:** Umbrella tracking issue spanning multiple in-progress PRs and kernel implementations; not a single fixable bug.

**Root Cause:** This is a tracking issue (not a bug report) for incrementally enabling FP8 and MXFP8 operations on XPU. Several memory ops (add/sub/mul/div, compare, normal) and GEMM ops (_scaled_mm with block scaling and MXFP8, _scaled_grouped_mm) are partially implemented (🟡) or missing. The gaps are in kernel implementations within torch-xpu-ops for arithmetic/comparison ops on FP8 dtypes, and GEMM ops for advanced scaling modes.

**Fix Strategy:** This is a multi-PR tracking issue. Individual sub-tasks are tracked via linked PRs (e.g., #2145 for add/sub/mul/div, #2154 for compare). Each unfinished item requires separate kernel implementations in torch-xpu-ops. No single agent action closes this issue — it is an umbrella tracker that must be resolved incrementally as sub-PRs land.

**Tokens:** model: claude-sonnet-4 | tokens: 37.5K | in: 3 | out: 373 | cache_read: 34.4K | cache_write: 2.7K | cost: $0.0262
Log: `agent-issue-2207-triaging-20260511-212839.log`