CXL IDE stream error if CXL device runs at gen5 speed and with non-zero segment

Teeio validator checks segment number returned from KM QUERY response. It works fine with PCIe Gen6 and 256B flit because CXL device KM QUERY response returns correct segment number.

But when link runs at gen5 or below, endpoint doesn't know which segment it is part of, so it always returns 0. If CXL device in fact is in non-zero segment, teeio validator will fail the check and fail entire IDE setup test.

Below is problematic code:

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[root@fuxiaogu-mobl1 bin]# git diff

diff --git a/teeio-validator/library/cxl_ide_test_lib/test_case/ide_km_common.c b/teeio-validator/library/cxl_ide_test_lib/test_case/ide_km_common.c

index 98bed2d..499470c 100644

--- a/teeio-validator/library/cxl_ide_test_lib/test_case/ide_km_common.c

+++ b/teeio-validator/library/cxl_ide_test_lib/test_case/ide_km_common.c

@@ -212,7 +212,8 @@ static bool do_query_port_index(cxl_ide_test_group_context_t *context,

port_index, dev_func, bus, segment, *max_port_index));

// Check if this port matches the target device

- return (dev_func == target_dev_func && bus == target_bus && segment == target_segment);

+ // return (dev_func == target_dev_func && bus == target_bus && segment == target_segment);

+ return (dev_func == target_dev_func && bus == target_bus);

}

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