intel / intel/rohd

filelist generation for SystemVerilog

Open
#683 0 comments 0 reactions 0 assignees View on GitHub
enhancement
Dominant language
Dart
Stars
489
Forks
88
Avg merge
3d 23h
Merged PRs (30d)
10

Description

### Motivation

While refactoring the API for SystemVerilog we realized we do not have a filelist export for multiple file output.

rohd-bridge also generates a filelist.f, maybe worth considering? see:
https://github.com/intel/rohd-bridge/blob/5cba1f5c9df2562c54ce55279a73ee7d71b48cc6/lib/src/bridge_module.dart#L991

### Desired solution

Add an option for generating appopriate collateral like a filelist.

### Alternatives considered

_No response_

### Additional details

_No response_

Contributor guide

Open the contributing guide

Research direction

Start by reading the SystemVerilog API refactoring work and the linked rohd-bridge example in lib/src/bridge_module.dart around line 991. Trace where multiple-file output is produced and determine the appropriate option boundary; done means the option generates an appropriate filelist.f or equivalent collateral for SystemVerilog output.

Written by the indexing model from the issue text.

Assessment

Tech stack
dart
Domain
build-system
Issue type
Feature
Difficulty
4/5
Estimated time
3-5 days
Activity status
Quiet
Clarity
Mostly clear
Newbie friendliness
45/100

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