Allow assignment merging in SystemVerilog between packed arrays and non-arrays when legal

### Motivation

There are cases where a packed array can safely be used in places where a normal `logic` can be used in generated SV. This could avoid a bunch of swizzling in generated outputs.

### Desired solution

Allow merging of signals across assignments between packed arrays and signals when there is a full assignment and the dimensions are safe to merge.

### Alternatives considered

_No response_

### Additional details

_No response_