`SystemVerilog.definitionParameters` does not enforce uniqueness with other names

### Describe the bug

It is possible to name a SystemVerilog parameter using `SystemVerilog.definitionParameters` with a name that conflicts with other names in that module definition (ports, reserved instance/signal names, etc.). This should not be allowed and uniqueness should be enforced.

### To Reproduce

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### Expected behavior

_No response_

### Actual behavior

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### Additional: Dart SDK info

_No response_

### Additional: pubspec.yaml

```yaml

```

### Additional: Context

_No response_