intel / intel/rohd

abs() produces a complex name

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#608 1 comment 0 reactions 0 assignees View on GitHub
enhancement
Dominant language
Dart
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489
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88
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3d 23h
Merged PRs (30d)
10

Description

### Motivation

signal.abs() produces a Verilog name '_b_add_const1.

It would be nice if it produces _twosComplement or something more meaningful like that

### Desired solution

add a .named() to the abs() return Logic that adds something more meaningful than _b_add_const1

### Alternatives considered

_No response_

### Additional details

_No response_

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