Dynamically renameable ports during code generation

### Motivation

Many of the least attractive names in generated output SystemVerilog are a result of combinations of unnamed signals that could not be optimized out. The resulting name is based on the name at the time of module construction, rather than at the time of generation, when a better name may have been selected. It would be nice if a generated unnamed signal could be smarter about combining other signal names during generation time.

### Desired solution

Allow some modules (e.g. `Add`, `BusSubset`, and `Swizzle`) to change their input/output names from the perspective of SV generation to more attractive names.

### Alternatives considered

_No response_

### Additional details

_No response_