Enable Const() to use an Enum as an argument, and name it appropriately

### Motivation

We often have Enums as constant integers that also need to be used as Const Logic.
While we can call the index of the enum, we lose its name and we'd like a way to have that abstraction
in the output Verilog along with the simpler way of constructing Const(enum) instead of Const(enum.index).

### Desired solution

I'd like to be able to use
```
cases(
Const(enum, width: w):

```
This may require changing both Const constructor as well as the cases code to deal with both retrieving the index
as well as adding the name to the case item.

### Alternatives considered

i tried modifying just Const constructor but the naming is still an issue.
I explored adding naming to the Combinational section of cases, where we can check the condition key.
Yet at this point it sees the wrapped enum as a Logic, so it may not be that simple to understand that this is
a Logic which is actually a Const initialized by an enum.

### Additional details

_No response_