Limit length of generated signal names

### Motivation

If you're not careful, it's possible to generate really really long names for signals in generated outputs (e.g. SystemVerilog). For example, if you use lots of & gates, you might get a signal "a_and_b_and_c_and_..." if you don't name any of the intermediates. Eventually, these could be thousands of characters long (or more!). Downstream EDA tools don't love that.

### Desired solution

Some way to limit the length of SystemVerilog signal names in generated outputs. Perhaps this should be a configurable option in `SystemVerilogSynthesizer`?

There's some consideration about how to best handle it, since you still need to have room for uniquification of signal names, so a straight truncation at the maximum alone is not sufficient.

### Alternatives considered

_No response_

### Additional details

_No response_