Attaching a packed array port to an unpacked array port of a submodule generates bad SV

### Describe the bug

The generated SV for assigning an unpacked array port to a packed array port in the parent module causes a direct connection. For example:

```SystemVerilog
module top(
input logic [2:0][3:0] a
);

// this is not ok, can't assign unpacked port to a packed port
submod sub(.a(a));

endmodule : top

module submod(
input logic [3:0] a [2:0]
);

endmodule : submod
```

### To Reproduce

Construct a hierarchy like described above

### Expected behavior

_No response_

### Actual behavior

_No response_

### Additional: Dart SDK info

_No response_

### Additional: pubspec.yaml

```yaml

```

### Additional: Context

_No response_