Mark dangling ports in module instantiations

### Motivation

Currently, if a port has a dangling port, the instantiation in generated verilog will create a `logic` to put on that port, then leave it floating. It would potentially be better to instead explicitly mark it as dangling in the generated output with a comment.

For example:
```SystemVerilog
.o(/*dangling output/*)
```

### Desired solution

When ports of (non-custom) modules are left dangling, instead of shoving a floating signal in, mark it as dangling.

### Alternatives considered

_No response_

### Additional details

It's important to ensure that the resulting solution is tool-friendly, lint-clean, etc.

Perhaps this should be an optional feature on the `Synthesizer`