Allow swizzles to be receivers of assignments in generated SystemVerilog for nets

### Motivation

It's legal in SystemVerilog for an assignment to be a swizzle:
```SystemVerilog
assign {a, b} = {c, d};
```

Currently ROHD will create an intermediate signal for logic nets, rather than do it in a single `net_connect` line.

### Desired solution

Enable the ROHD SystemVerilog generation to merge assignments between swizzles.

### Alternatives considered

_No response_

### Additional details

_No response_