Partial assignment of `Logic` indices

### Motivation

In SystemVerilog and some other HDLs/generator frameworks (e.g. Chisel) there are APIs for assigning an element/range of a bus/array where the index is itself a signal. This implies significant muxing hardware, but has a nice API. ROHD should have a similar API.

### Desired solution

Perhaps some sort of expansion on `withSet` APIs to accept `Logic` in addition to just `int`.

### Alternatives considered

_No response_

### Additional details

_No response_

Start by reviewing the existing withSet APIs and how Logic represents bus or array indices. The desired outcome is an API that supports partial element or range assignment with a Logic index, including the associated muxing behavior; the issue does not name specific files or tests.

Written by the indexing model from the issue text.