Support VHDL
Open
enhancement
help wanted
- Dominant language
- Dart
- Stars
- 489
- Forks
- 88
- Avg merge
- 3d 23h
- Merged PRs (30d)
- 10
Description
### Motivation
VHDL is a popular alternative to SystemVerilog
### Desired solution
The capability to generate VHDL in addition to SystemVerilog, as well as instantiate external VHDL modules instead of only SystemVerilog (including for cosimulation)
### Alternatives considered
_No response_
### Additional details
_No response_
Contributor guide
Assessment
This issue has not been assessed yet.