Improve documentation on instantiating SystemVerilog modules
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- Dart
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Description
The documentation for instantiating other things in SystemVerilog is not clear enough and could really use some examples.
https://intel.github.io/rohd-website/docs/external-modules/
It would be nice to cover:
- `ExternalSystemVerilogModule`
- `CustomSystemVerilog`
- `InlineSystemVerilog`
The example in ROHD Cosim is a little better than the user guide, for example:
https://github.com/intel/rohd-cosim#using-rohd-cosim
Brought to attention by "grav" on Discord:
https://discord.com/channels/1001179329411166267/1170668309973315645
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