CSRs create a lot of modules

### Motivation

When we handle large register sets, we encounter a lot of overhead because each register becomes a module. This impacts internal memory and simulation speed. Much of this is recovered when we use a SystemVerilog simulator on the output, but it would be nice to see less memory and speed overhead in the ROHD system itself.

### Desired solution

Explore inlining CSR registers and see if we can take advantage in both memory and simulation.

### Alternatives considered

_No response_

### Additional details

_No response_