[Bug] Axi4MemorySubordinate: multi-beat write bursts store only the last beat's data at every address

## Bug Description

`Axi4SubordinateMemoryAgent._captureWriteData` reads `wIntf.data.value` to
build each write beat's data packet. However, the W-channel monitor fires
**once per burst** with all beats aggregated in `packet.data` via
`_dataBuf.rswizzle()`. At callback time `wIntf.data.value` holds only the
**last beat's data**, silently corrupting every address in a multi-beat write
burst.

Two related issues are also present:

1. **Stale beat-0 on simultaneous AW+W** — `_receiveWrite` can enqueue a
beat-0 packet when AW and the first W beat arrive in the same cycle.
`_captureWriteData` does not clear this entry, leaving a duplicate.

2. **Queue not cleared after `_respondWrite`** — `_writeDataQueue` is never
cleared after a write response is sent, causing stale entries to corrupt
subsequent burst transactions.

## Fix

PR #289 contains a surgical fix:
https://github.com/intel/rohd-hcl/pull/289

Changes are limited to `axi4_memory_subordinate.dart` — unpack beats from
`packet.data` using `getRange(i*dw, (i+1)*dw)`, clear the queue before
unpacking, and clear after `_respondWrite` completes. A new test
(`multi-beat write burst stores each beat at its own address`) is also included.