Shifting by constants produces complex names when using << versus >>>

### Motivation

```dart
final tShift = (t << 1).named('tShift');
final tBarShift = (~t << 1).named('tBarShift');
final zBarShift = (~z >>> 1).named('zBarShift');
final gBarShift = (~g >>> 1).named('gBarShift');
```
produces
```Verilog
assign tShift = t << _shiftAmount_const_8_h1;
assign tBarShift = ~t << _shiftAmount_const_8_h1_0;
assign zBarShift = ~z >> 1'h1;
assign gBarShift = ~g >> 1'h1;
```

### Desired solution

It would be nice to see
```Verilog
assign tShift = t << 1'h1;
```

### Alternatives considered

_No response_

### Additional details

_No response_

Reproduce the Dart example from the issue and compare the generated Verilog for left and right shifts, especially the constant forms. Trace the shift-expression code-generation path and verify that constant shifts produce the desired compact Verilog without unnecessary generated names.

Written by the indexing model from the issue text.