Add testing for clock-divider logic with cosimulation

A bug exists in ROHD related to clock dividers:
https://github.com/intel/rohd/issues/191

The logic in cosimulation is similar to the logic of sequential logic in a plain ROHD simulation. We should review that a similar bug does not exist in ROHD Cosim, and add tests that clock dividers behave as expected in cosimulation. This may require waiting for the ROHD issue to be resolved first.