Enable `Module`s to be run in SystemVerilog simulators
Open
enhancement
help wanted
- Dominant language
- Dart
- Stars
- 29
- Forks
- 6
- PR merge metrics
- No merged PRs in 30d
Description
### Motivation
It might be desirable to run a ROHD test/testbench on a ROHD module in a SystemVerilog simulator. For example, perhaps a very large module running a long-running test could run faster in another SystemVerilog simulator than in the ROHD simulator (e.g. Verilator is multithreaded).
### Desired solution
Add some simple automation that can be applied to a `Module` so that it can be run in `Cosim`, including generation of the SystemVerilog for that module and wrapping, so that it is as seamless as possible.
### Alternatives considered
_No response_
### Additional details
_No response_
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