Build an annotation-based cosim-wrapper code generator
Open
enhancement
- Dominant language
- Dart
- Stars
- 29
- Forks
- 6
- PR merge metrics
- No merged PRs in 30d
Description
It can be tedious to build a cosim wrapper for a SystemVerilog module for cosimulation. Since enough information is provided anyways to build and simulate the module, it would be nice to have an annotation-based code generator which could build the wrapper with all ports already added.
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Assessment
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