Refactor how default value for vectorization switch is selected in intel/llvm#2402

There is a comment from @bader:

> @AlexeySachkov, I would prefer if we disable vectorizers only for SPIR target as I noted here. So if Xilinx FPGA uses different triple, it can still control the default behavior. NOTE: NVPTX, doesn't completely disables the vectorizer - https://github.com/intel/llvm/blob/sycl/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h#L65. It's not clear what is the impact on performance for NVPTX.

Which needs to be applied