intel / intel/llvm

Cache control hint test issues.

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Description

https://github.com/intel/llvm/blob/8ab28e0d43a0d9bdff7210b39d04b891676009ee/sycl/test/check_device_code/extensions/properties/properties_cache_control.cpp#L61-L71

This code is supposed to check cache hints for load operation, but test only does one store. The same issue exists in other "read" checks.
All checks in this test are doing only store operation.
https://github.com/intel/llvm/blob/8ab28e0d43a0d9bdff7210b39d04b891676009ee/sycl/test/check_device_code/extensions/properties/properties_cache_control.cpp#L148-L152
This is the only place where the test loads with cache hints.

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