intel / intel/llvm

[SYCL] Refactor and Upstream Clang TargetInfo for SYCL

Open
#19,025 0 comments 0 reactions 0 assignees View on GitHub
enhancement upstream
Dominant language
LLVM
Stars
1.5k
Forks
854
Avg merge
3d 17h
Merged PRs (30d)
137

Description

### Is your feature request related to a problem? Please describe

The Clang `TargetInfo` used for SYCL seems to contain a good deal of duplication for SPIR, SPIRV targets. In order to upstream this part of the codebase some refactoring is needed. As @Naghasan mentions

> E.g. AMD has one TargetInfo and NV has 2 (for the 32 and 64 variants) and that enough to support all host...

For more context see https://github.com/intel/llvm/pull/18859

### Describe the solution you would like

Refactor and upstream SPIR, SPIRV target info.

Contributor guide

Open the contributing guide

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.