Remove FPGA features from DPC++

With the launch of Altera as a separate entity, oneAPI DPC++ will concentrate on support for GPU and CPU devices. Altera will continue to provide FPGA support through their dedicated FPGA software development tools. You can read more about this in the deprecation notice at the top of the [oneAPI DPC++ release notes](https://www.intel.com/content/www/us/en/developer/articles/release-notes/intel-oneapi-dpc-c-compiler-release-notes.html). As a result, the following features are scheduled for removal:

1. We will remove the [sycl_ext_oneapi_annotated_arg](https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_oneapi_annotated_arg.asciidoc) extension. We added this in order to decorate kernel arguments with properties, which were mostly specific to FPGA. It is possible that non-FPGA code could use this extension to decorate kernel arguments with the `alignment` or `unaliased` properties, though it would be more common to use [sycl_ext_oneapi_annotated_ptr](https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_oneapi_annotated_ptr.asciidoc) for this purpose because these properties apply only to pointers. (Note the difference is “arg” vs. “ptr”.) We plan to *keep* supporting sycl_ext_oneapi_annotated_ptr. Therefore, code using sycl_ext_oneapi_annotated_arg should migrate to use sycl_ext_oneapi_annotated_ptr instead.

2. We will remove the [sycl_ext_intel_usm_address_spaces](https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_usm_address_spaces.asciidoc) extension. This extension adds address spaces named `ext_intel_global_device_space` and `ext_intel_global_host_space` as well as `multi_ptr` aliases named `device_ptr` and `host_ptr` (and some other variants). Although it’s possible to use these on non-FPGA devices, they provide no benefit. Therefore, code using this extension should use the standard SYCL address spaces instead.

3. We will remove the following compiler command line options which are all specific to FPGA:

* `-fsycl-targets=spir64_fpga`
* `-fsycl-targets=spir64_fpga-unknown-unknown`
* `-fintelfpga`
* `-fsycl-help=fpga`
* `-fsycl-link=early`
* `-fsycl-link=image`
* `-reuse-exe`
* `-fhls`
* `-Xsycl-target-backend=spir64_fpga`

4. We will remove “fpga” from the device types recognized by the [ONEAPI_DEVICE_SELECTOR](https://github.com/intel/llvm/blob/sycl/sycl/doc/EnvironmentVariables.md#oneapi_device_selector) environment variable.

5. We will remove “fpga” from the device types recognized by the [SYCL_DEVICE_ALLOWLIST](https://github.com/intel/llvm/blob/sycl/sycl/doc/EnvironmentVariables.md#sycl_device_allowlist) environment variable.

6. We will remove all of the following extensions that are specific to FPGA devices:

* https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_buffer_location.asciidoc
* https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_dataflow_pipes.asciidoc
* https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_fpga_device_selector.asciidoc
* https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_fpga_lsu.md
* https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_fpga_reg.md
* https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/supported/sycl_ext_intel_mem_channel_property.asciidoc
* https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_intel_data_flow_pipes_properties.asciidoc
* https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_intel_fpga_task_sequence.asciidoc

7. We will remove two properties from the [sycl_ext_oneapi_device_global](https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_oneapi_device_global.asciidoc) extension that are specific to FPGA named `init_mode` and `implement_in_csr`.