crc: Using gp and tp in riscv64 may cause problems

Testing in Ceph revealed problems with the use of gp and tp: https://github.com/ceph/ceph/pull/69908

The same issue exists in isa-l: https://github.com/intel/isa-l/blob/7c3479e0a9dac17f448603ec1ad64c7c625f530c/crc/riscv64/crc16_t10dif_copy_vclmul.S#L186

When this was mentioned before, I didn't know the specific scenario where it would cause problems (https://github.com/intel/isa-l/pull/350#discussion_r2725398864), but now it seems it needs to be fixed.

Start with crc/riscv64/crc16_t10dif_copy_vclmul.S at the referenced line and compare the behavior described in Ceph PR 69908 and the earlier isa-l discussion. Determine the affected RISC-V register usage, then verify the fix with the repository's relevant CRC build or test path.

Written by the indexing model from the issue text.