E810-XXVDA4T: Given only a PPS signal, EEC DPLL locks, but PPS DPLL does not.

For my application, I am using only a PPS signal fed into one of the SMA/U.FL Inputs on an E810-XXVDA4T.

I've configured the SMA/U.FL ports per the 1.7 user guide.

`cat /sys/kernel/debug/ice/$DEVICE/cgu` returns:

```
Found ZL80032 CGU
DPLL Config ver: 1.3.0.1
DPLL FW ver: 6201

CGU Input status:
| | priority | |
input (idx) | state | EEC (0) | PPS (1) | ESync fail |
----------------------------------------------------------------
CVL-SDP22 (0) | invalid | 8 | 8 | N/A |
CVL-SDP20 (1) | invalid | 255 | 3 | N/A |
C827_0-RCLKA (2) | invalid | 4 | 4 | N/A |
C827_0-RCLKB (3) | invalid | 5 | 5 | N/A |
SMA1 (4) | valid | 1 | 1 | N/A |
SMA2/U.FL2 (5) | invalid | 2 | 2 | N/A |
GNSS-1PPS (6) | invalid | 0 | 0 | N/A |

EEC DPLL:
Current reference: SMA1
Status: locked_ho_acq

PPS DPLL:
Current reference: SMA1
Status: freerun
Phase offset [ps]: 1839840204
```

The PPS DPLL will `freerun` for 10.5-12 seconds, switch to a `locked` state for .5-1.2 seconds, and then return to the `freerun` state. Its Phase offset will drift up if possible, and down if negative (positive feedback loop). It will drift past the zero crossing, as well as the +/- 500000000000ps values but will roll over at those values.

The EEC DPLL will remain in a `locked_ho_acq` during this entire process.

This behavior also remains constant if using the SMA1/2 and U.FL2 connections all configured as RX ports.
This behavior is consistent across two different cards in multiple different computers.

Is there something wrong with my hardware setup? An issue with the firmware? An issue with the driver?