intel / intel/FSP

SMBIOS Cache Information Hob - Coffeelake

Open
#75 0 comments 0 reactions 0 assignees View on GitHub
Dominant language
C
Stars
359
Forks
142
PR merge metrics
No merged PRs in 30d

Description

I am using GUID to get SMBIOS cache information hob, but it only returns the L1 cache information. L2 and L3 cache information resides in next addresses after L1 cache information. So I had to manually write their addresses.

Can you define another GUID for L2 and L3? Or can you show me a workaround in case I miss something?
Thanks,

Contributor guide

Open the contributing guide

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.