TigerLake FSP problems with Tiger Lake UP3 RVP

Tiger Lake FSP has problems with booting Tiger Lake UP3 RVP (DDR4 SODIMM design):

Tried MinPlatform with recently published TigerlakeOpenBoard and I get the following results using GCC5 compiler:
1. Building for FSP API mode:
- Memory Init fails quickly due to HDA GPIO configuration error (disabling HDA workarounds the problem)
- If the above is resolved then the FSP is stuck at `IgdIommuOverride` (at least this is the last log on the serial port with debug FSP binary)
2. Building for FSP wrapper mode:
- The platform resets after entering `PeiFspSaPolicyInitPreMem`. After the reset the last log is also an entrance to `PeiFspSaPolicyInitPreMem` but this time the platform hangs.

I experienced similar HDA problems with coreboot. Although I can get past FSP-M, the platform resets in CPU init routine during MCE registers clearing (https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/MW44TIEMFMVDWPVCAFPE2QUFXXGZYYAX/)
The errors may be related to the fact that port is done for LPDDR4 variant and I am testing DDR4 SODIMM.

@pietrushnic