intel / intel/FSP

ApolloLakeFspBinPkg[MR6] configures PCIe Root Port's DCTL[MPS]

Open
#56 0 comments 0 reactions 0 assignees View on GitHub
Dominant language
C
Stars
359
Forks
142
PR merge metrics
No merged PRs in 30d

Description

FSP configures the effective Max Payload Size for PCIe Root Ports (and probably other integrated PCIe devices). This seems wrong, because only the OS drivers for PCIe devices know the target of transactions and can decide the maximum payload size on the route.
Please fix that. Or add an option to FSP to disable its OS features. It's obvious that having unnecessary features in FSP only increases the amount of things that can go wrong (cf. #55). Such errors make the use of FSP much more expensive than a custom implementation.

Contributor guide

Open the contributing guide

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.