FSP DRAM configuration for memory with only single channel

Hello,
We're using the custom hardware (let's call it BRC) based on the Apollo lake's Leaf hill crb.

BRC -> 4 x 16 gib = 8 GiB of memory(4 dual-rank chips organized as 512 M by 32 bits.). This configuration i am able to boot up.

Now, we have new variant of this board (just the memory downsized) with 1 x 8 gib = 1 GiB of LPDDR4 memory (1 single-rank chip organized as 256 M by 32 bits.).
(the other 3 chips were not populated).

(Note: Micron memory is being used : MT53E256M32D2DS-053 in both cases).

This is my DRAM config for these two boards:
8 GiB of memory(4 dual-rank chips organized as 512 M by 32 bits):
Channeln (n = 0, 1, 2, 3):
RankEnable :0x1
DeviceWidth :0x1
DramDensity :0x4
Option :0x3
OdtConfig :0x0
TristateClk1 :0x0
Mode2N :0x0
OdtLevels :0x0

1 GiB of memory(1 single-rank chip organized as 256 M by 32 bits):
Channel0:
RankEnable :0x1
DeviceWidth :0x1
DramDensity :0x2
Option :0x3
OdtConfig :0x0
TristateClk1 :0x0
Mode2N :0x0
OdtLevels :0x0

Channeln (n = 1, 2, 3):
RankEnable :0x0

With this configuration, SBL is not getting past fspmemoryinit(). I am using the FSP debug library from Intel. From that, i am not quite sure what's going wrong. Does anyone of you have experience of using only single channel memory configuration?

I am enclosing the beyond compare snapshot between these two versions (working 4-channel board and single channel board).
Also enclosing the console log for this single channel board. Any leads on this will be really helpful.
[brc3-1gb-fsp-debug-only-RankEnable-disabled.txt](https://github.com/intel/FSP/files/4877081/brc3-1gb-fsp-debug-only-RankEnable-disabled.txt)


Regards,
Mahesh.