intel / intel/FSP

Comet Lake: Changed description of Serial Io Device Modes

Open
#18 0 comments 0 reactions 0 assignees View on GitHub
Dominant language
C
Stars
359
Forks
142
PR merge metrics
No merged PRs in 30d

Description

I hope you don't mind questions about FSP versions that didn't make it into this repo yet (if you do, just tell me).

We have here [new UPD headers](https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h#n757) for Comet Lake. Most of the options are very similar to those of the Coffee Lake FSP. One change resulted in [some confusion](https://review.coreboot.org/#/c/31284/15/src/soc/intel/cannonlake/include/soc/serialio.h@35), though: For the serial i/o mode options we had for CFL (SerialIoDevMode):

0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode)

which is now for CML (SerialIoUartMode amongst others):

0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit

So here is the question: Beside the additional value 4, did any semantics change for the values 0 to 3? or was it only the description that changed?

Contributor guide

Open the contributing guide

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.