Minimize TLB pressure
Open
- Dominant language
- Rust
- Stars
- 1.5k
- Forks
- 132
- Avg merge
- 1d 14h
- Merged PRs (30d)
- 39
Description
We are currently identity-mapping using these page sizes:
| Architecture | Page Size |
| ------------- | ---------:|
| AArch64 | 4 KiB |
| 64-bit RISC-V | 1 GiB |
| x86-64 | 2 MiB |
It would be good to use the larges page size possible on each architecture instead.
This would make the memory layout simpler while minimizing TLB pressure.
Contributor guide
No contributing guide indexed for this repository
Assessment
This issue has not been assessed yet.