Delay model generation: can't characterize signExt because of Yosys optimization

In XLS's automatic delay model generation, a parameterized XLS op is instantiated by itself between a bank of input registers and a bank of output registers, and then synthesized in for the target platform, and timed.

Even though sign extension involved no logic cells, we should be able to time the extra delay for fanning out the sign bit (from one input register) to a number of sinks (output registers).

However, Yosys will trim the number of output registers to match the number of input registers, and then implement the fanout between the MSB output register and the top-level outputs, which is not the path that we want to time in our setup.

We have not yet found a way to disable this optimization.