verilog bazel rules should emit System/VerilogInfo

It seems that currently `dslx/ir_verilog` rules are connected to `bazel_rules_hdl`'s `verilog_library` thru brick and mortar files, see:
https://github.com/google/xls/blob/75930f7667fdc725d987bd6d02b8719b35c9f6dd/xls/examples/BUILD#L407-L412

It'd be nice to leverage instead structured bazel types like `VerilogInfo`: https://github.com/hdl/bazel_rules_hdl/blob/main/verilog/providers.bzl#L19, it could also allow simulation rules to ask for specific variant of (system)verilog depending of their frontend capabilities.