Check failed: cycle_map_.contains(node) Tried to remove a node from a schedule that it doesn't contain

While I understand the code generation with ram support is very experimental;I wanted to ask if you see something wrong with this example that produces the following:

pipeline_schedule.cc:249] Check failed: cycle_map_.contains(node) Tried to remove a node from a schedule that it doesn't contain
*** Check failure stack trace: ***
0x561e7a1f0599: xls::logging_internal::LogMessage::Flush()
0x561e7a1f076d: xls::logging_internal::LogMessageFatal::~LogMessageFatal()
0x561e79c5bb7d: xls::PipelineSchedule::RemoveNode()
0x561e79c5b1f9: xls::SchedulingWrapperPass::RunInternal()
0x561e79b3eb24: xls::PassBase<>::Run()
0x561e79b410d4: xls::CompoundPassBase<>::RunNested()
0x561e79b3e9e8: xls::PassBase<>::Run()
0x561e79b45dc7: main
0x7f2999423510: [unknown]

The IR src: [ccTop_opt.ir.txt](https://github.com/google/xls/files/10787478/ccTop_opt.ir.txt)

codegen_main ccTop.ir --module_name=xlscc_ccTop_proc --generator=pipeline --delay_model=unit --pipeline_stages=3 --clock_period_ps=4000 --ram_configurations=ram:1RW:memory__read_request:memory__write_response --io_constraints=memory__read_request:send:memory__write_response:recv:2:2 --reset=rst --reset_data_path=true --reset_active_low=false --reset_asynchronous=true --flop_inputs=false --flop_single_value_channels=false --flop_outputs=false --add_idle_output=false --streaming_channel_data_suffix=_data --streaming_channel_ready_suffix=_ready --streaming_channel_valid_suffix=_valid --use_system_verilog=true --output_verilog_line_map_path=ccTop.verilog_line_map.textproto --output_schedule_path=ccTop.schedule.textproto --output_verilog_path=ccTop.sv --output_signature_path=ccTop.sig.textproto --output_block_ir_path=ccTop.block.ir

Thanks for any hints or guidance.