Improve channel port names and order in DSLX

Port names in verilog associated with channels in DSLX have long obscure names. They should be improved. Furthermore, the order in the verilog module is arbitrary, related ports should be grouped together in a deterministic order (order they appear in the DSLX proc?).

Scoping channels to procs might help with this by avoiding the need to prefix the channel names with module name.

Example:

```
pub proc foo {
in0_ch: chan in;
in1_ch: chan in;
out0_ch: chan out;
out1_ch: chan out;

init { () }

config (in0: chan in,
in1: chan in,
out0: chan out,
out1: chan out) {
(in0, in1, out0, out1)
}

next(tok: token, state: ()) {
let (tok, _) = recv(tok, in0_ch);
let (tok, _) = recv(tok, in1_ch);
let tok = send(tok, out0_ch, u32:123);
let tok = send(tok, out1_ch, u32:11);
()
}
}
```

Build verilog command:

```
bazel-bin/third_party/xls/dslx/ir_converter_main /tmp/foo.x > /tmp/foo.ir &&
bazel-bin/third_party/xls/tools/opt_main --top=__foo__foo_0_next /tmp/foo.ir > /tmp/foo.opt.ir &&
bazel-bin/third_party/xls/tools/codegen_main /tmp/foo.opt.ir --pipeline_stages=1 --delay_model=unit --reset=rst
```

Resulting verilog:

```
module __foo__foo_0_next(
input wire clk,
input wire rst,
input wire [31:0] foo__in0,
input wire foo__in0_vld,
input wire [31:0] foo__in1,
input wire foo__in1_vld,
input wire foo__out0_rdy,
input wire foo__out1_rdy,
output wire [31:0] foo__out0,
output wire [31:0] foo__out1,
output wire foo__out0_vld,
output wire foo__out1_vld,
output wire foo__in0_rdy,
output wire foo__in1_rdy
);
...
```