Enhance simulator to support '0' latency input and output delays for circuits generated with pipeline

Currently, to conform with the testbench in the simulator, the `--flop_inputs` and the `--flop_outputs` must be set to `true` and the only valid values for `--flop_inputs_kind`/`--flop_outputs_kind` are: "flop" and skid".

Enhance the simulator to support:

1. `--flop_inputs=false` and `--flop_outputs=false`
1. `--flop_inputs=true --flop_inputs_kind=zerolatency` and `--flop_outputs=false --flop_outputs_kind=zerolatency`

Suggest adding the properties to: [module_signature.proto](https://github.com/google/xls/blob/main/xls/codegen/module_signature.proto) and modifying [module_simulator.cc](https://github.com/google/xls/blob/main/xls/simulation/module_simulator.cc#L186).