Support other options for `flop_input_kind` when generating Verilog for samples with non-blocking receives.

Non-blocking receives introduce non-deterministic behavior (more than one set of possible valid results).

Currenlty, to facilitate the matching of the results in the fuzzer of other stages to the simulation stage, samples with non-blocking receives generate Verilog with `flop_input_kind=zerolatency` to mimic the behavior evaluated in other stages in the fuzzer.

This issue is to track the support for other options for the `flop_input_kind` argument: e.g. `flop` and `skid`. Note that these options introduce delay which triggers the non-determinism of the non-blocking operation.