Add waveform traces output to testbench to simulator

Currently, XLS supports iverilog for simulating verilog module with a testbench. When simulating iverilog, the waveform of the testbench can be created for viewing by other open source tools (e.g. [gtkwave](https://gtkwave.sourceforge.net/)).

To produce the waveform traces, the following can be added to the initial block of the testbench.
```
$dumpfile("some_file_name.vcd");
$dumpvars(0, test_bench_module_name);
```

Then, viewed by gtkwave:
```
gtkwave some_file_name.vcd
```