Optimize priority_sel with same values as cases

With a priority select with the same value for the cases, e.g.
```
x23: bits[27] = priority_sel(x10, cases=[x1, x1, x1, x1, x1], id=80, pos=[(0,21,29)])
```

remains untouched after optimization.
```
x23: bits[27] = priority_sel(x10, cases=[x1, x1, x1, x1, x1], id=80, pos=[(0,21,29)])
```

We can perform an optimization that reduces the amount of cases, and, thus the bits for the selector. The latter would enable less area in the HW design.

```
x11: bits[1] = or_reduce(x10)
x23: bits[27] = priority_sel(x11, cases=[x1], id=80, pos=[(0,21,29)])
```
Note that, although synthesis tools may perform these types/style of optimizations, from an XLS perspective, it would produce more readable Verilog and may enable quicker JIT execution.